1. Field of the Invention
The present invention relates to a microcomputer, and more particularly to a microcomputer whose instruction word length is uniform.
2. Description of the Prior Art
FIG. 8 is a block diagram showing an arrangement of a conventional microcomputer. In FIG. 8, numeral 14 represents a data bus, 15 designates an address bus, 16 depicts a control signal bus, 17 denotes a first shifter, and 18 indicates an instruction first-reading buffer. Further, numeral 20 is a first pointer, 21 represents a second pointer, 22 denotes a first adder, 23 designates a second adder, 24 depicts a third adder, 25 indicates a first decoder, 26 is a second decoder, and 27 denotes a bus timing generating means. Moreover, numeral 28 is an address register, 29 represents a fourth adder, 36 designates an ALU (arithmetic and logic unit), 37 denotes a register file, 70 depicts a second shifter, 71 is a bus interface means, 72 is an instruction interpreting means, 73 is a data expansion means and 74 designates an executing means.
The data bus 14 is a bus for reading an instruction word from a memory or the like, not shown, into the bus interface means 71, the address bus 15 is a bus for supplying the address data of the address register 28 to a memory or the like, and the control signal bus 16 is a bus for supplying a writing/reading signal (R/W) to a memory or the like. The first shifter 17 of the bus interface means 71 comprises gates 17a to 17c whereby an instruction word with 1-word length on the data bus 14 is stored in predetermined word positions 18a to 18c of the instruction first-reading buffer 18 under the gate control. The instruction first-reading buffer 18 is a data buffer which can temporarily store an instruction word with 3-word length, whereby a 1-word length instruction word is stored in the word position 18a to 18c selected by the gates 17a to 17c of the first shifter. The first pointer 20 indicates the number of the 1-word length instruction words stored in the instruction first-reading buffer 18. For example, the number is 0 to 3. The second pointer 21 indicates the word position of the instruction word to be read out at the next time. The first adder 22 is, for example, a 2-bit adder for calculating the sum (addition) of the contents of the first and second pointers 20 and 21 and has a carrier output. The second adder 23 adds +1 to the first pointer (content) 20 when a 1-word length instruction word is read in the instruction first-reading buffer 18 through the data bus 14, adds -1 thereto when an instruction word is read out from the instruction first-reading buffer 18 or the read-in and read-out of a 1-word length instruction word and a 2-word length instruction word are simultaneously performed, adds -2 thereto when a 2-word length instruction is read from the instruction first-reading buffer 18, and adds +0 thereto when the read-in and read-out of a 1-word length instruction word is simultaneously effected. The third adder 24 adds +1 to the second pointer 21 when a 1-word length instruction word is read out from the instruction first-reading buffer 18 and adds +2 thereto when a 2-word length instruction word is read out from the instruction first-reading buffer 18.
The first decoder 25 decodes the output of the first adder 22 and controls the gates 17a to 17c of the first shifter 17 to ON. For example, when the output of the first adder 22 is "0" or "3", the gate 17a of the first shifter 17 is turned ON, and when the output thereof is "1" or "4", the gate 17b is turned ON, and when the output thereof is "2", the gate 17c is turned ON. The second shifter 70 comprises gates 70a to 70c the control of which allows a 2-word length instruction word to be read out from the word positions 18a to 18c of the instruction first-reading buffer 18 in the instruction interpreting means 72 or the data expansion means 73. The second decoder 26 decodes the output of the second pointer 21 to control the second shifter 70. For example, when the output of the second pointer 21 is "0 ", the gates 70a and 70b are simultaneously turned ON, and when the output thereof is "1", the gates 70b and 70c are turned ON, and when the output thereof is "2", the gates 70a and 70c are turned ON. The bus timing generating circuit 27 puts data such as an address and R/W on the address bus 15 and the control signal bus 16 at adequate timings. The address register 28 keeps addresses and indicates the address of an instruction word stored in a memory area of a memory, not shown. The fourth adder 29 adds +2 whenever the instruction word of the contents of the address register 28 is read in the bus interface means 71. The instruction interpreting means 72 interprets the instruction word from the bust interface means 71 to control the executing means 74. The data expansion means 73 sign-expands 2-word length data from the instruction first-reading buffer 18 of the bus interface means 71 and the executing means 74 executes the calculation indicated by the instruction interpreting means 72. The ALU 36 performs the arithmetic calculation, and the register file 37 is constructed with a program counter, general-use register and others and stores data for the calculation.
FIG. 9 shows a detailed example of the instruction word used in a conventional microcomputer. In FIG. 9, (a) indicates a format of an instruction word which does not include a field of offset data or immediate data and which comprises an identification field 80a (10 to 15 in bit number) and a register field 80b (0 to 9 in bit number). The register field 80b is further divided into a register field 1 (5 to 9 in bit number) and a register field 2 (0 to 4 in bit number). In FIG. 9, (b) shows a format which includes a field of a 1-word length immediate data or offset data and which has a 1-word length data field 80d (0 to 15 in bit number) and has the information that a 1-word length data is included in an identification field 80a (26 to 31 in bit number). In FIG. 9, (c) shows a format of an instruction word which has a 2-word length data field 80d (0 to 31 in bit number), wherein a data field 80d is further divided into a data field 1 (16 to 30 in bit number) and a data field 2 (0 to 15 in bit number) and an identification field 80a (42 to 47 in bit number) has the information that a 2-word length data is included. Further, in FIG. 9, (d) shows a format of an instruction word on a program which has 2-word length immediate data "IMM1.phi.L, IMM1.phi.H". To an identification field 80a there is inputted an "ADD" data, and to a register field 1 of a register field 80b there is inputted a register number RX.
FIG. 10 is a time chart showing an operation of a conventional microcomputer. In FIG. 10, (a) shows a clock signal which acts as a reference, (b) shows an operating state of the first pointer 20, (c) shows an operating state of the second pointer, and (d) shows an operating state of the address register 28.
Secondly, a description will be made hereinbelow in terms of the conventional microcomputer. First, the summary of the operation will first be described and the detailed operation will then be described. In the case of performing ADD RX, IMM1.phi., that is, in the case of executing an instruction that the sum of the data of the register number RX and the immediate data of IMM1.phi. is calculated and stored in the register number RX, this instruction word takes the instruction word format on the program as illustrated in FIG. 9. To the lower-address identification field 80a there is inputted the information having "ADD" and the immediate data corresponding to a 2-word length, to the register field 1 of the register field 80b there is inputted the register number RX, to the register field 1 of the register field 80b there is inputted the low-order data "IMM1.phi.L" of "IMM1.phi.", and to the data field 2 of the data field 80d there is inputted the high-order data "IMM1.phi.H" of "IMM1.phi.". This instruction word of ADD RX, IMM1.phi. is read from the memory area of a memory indicated by the address of the memory address register 28 of the bus interface means 71 into the word positions 18a to 18c of the instruction first-reading buffer 18 indicated by the first pointer 20, each of which has one word length, and read out from the word positions 18a to 18c of the instruction first-reading buffer 18, indicated by the second pointer 21, at every 2 words. The instruction interpreting means 72 reads and decodes the instruction data by one word in order from the low address in FIG. 9(d), for example. Since the identification field 80a is "ADD", the first instruction word is determined as an addition instruction, and since it has 2-word immediate data "IMM1.phi.L, IMM1.phi.H", the request of these immediate data is made with respect to the bus interface means 71 through the executing means 74. When the intermediate data is read out from the instruction first-reading buffer 18 of the interface means 71, the instruction interpreting means 72 causes the 2-word length immediate data to pass through the data expansion means 73 so as to be added to the data of the register number RX in the register file 37 in the ALU 36 under the control of the executing means 74, the addition result being stored in the register number RX.
Further, the detailed operation of the conventional microcomputer will be described with reference to FIG. 10. First, let it be assumed that the content of the first pointer 20 is "1", the content of the second pointer 21 is "1", and the above-mentioned instruction word ADD RX, IMM1.phi. is executed. At the time T1, the executing means 74 requests a 1-word length instruction word with respect to the bus interface means 71. Since at this time the content of the first point 20 is "1", the bus interface means 71 decides that the instructed word requested by the executing means 74 has already been read in the word position 18b of the instruction first-reading buffer 18 and hence decodes the content "1" of the second pointer 21 through the second decoder 26 and turns on the gate 70b of the second shifter 70 whereby the 1-word length instruction "ADD RX" is read out from the word position 18b of the instruction first-reading buffer 18 to the instruction interpreting means 72. At the same time, in the bus interface means 71, since the word positions 18a, 18c (2 words) of the instruction first-reading buffer 18 become vacant, the preparation for reading the next instruction word is made. The instruction interpreting means 72 decodes the 2-word immediate data information and and "ADD" of the identification field 80a after the instruction read from the word position 18b of the instruction first-reading buffer 18 of the bus interface means 71 and further decodes the register number RX of the register field 1 of the register field 80b, thereby controlling the executing means 74 and the data expansion means 73. Thereafter, since the 1-word length instruction word is read from the instruction first-reading buffer 18, the content of the first pointer 20 of the bus interface means 71 is added (subtracted) by -1 so as to become "0", and the content of the second pointer 21 is added in the third adder 24 to become "2".
At the time T2, the executing means 74 requests "IMM1.phi.L (low-order data), IMM1.phi.H (high-order data)" of the 2-word length immediate data "IMM1.phi.", which belong to the above-mentioned instruction word, with respect to the bus interface means 71. In response to the request, the bus interface means 71 decides that the immediate data is not read in the instruction first-reading buffer 18 because the content of the first pointer 20 is "0" and hence, causes the executing means 74 to assume a waiting state. Thereafter, the 1-word immediate data "IMM1.phi.L" of the address PAR indicated by the address register 27 is read from a memory (not shown) through the data buss 14 and the gate 17c of the first shifter 17 in the word position 18c of the instruction first-reading buffer 18. Then, +1 is added to the content of the first pointer 20 in the second adder 23 so as to become "1". The word position 18c of the instruction first-reading buffer 18 in which the immediate data of the instruction word is read is determined in accordance with the output of the first adder 22. That is, the content "0" of the first pointer 20 is added to the content "2" of the second pointer 21 so that 0+2=2 is decoded in the first decoder 25 so as to select the gate 17c of the first shifter 17.
At the time T3, the bus interface means 71 decides that the instruction first-reading buffer 18 is vacant (because the content of the first pointer 20 is "1") and starts the read-in of the immediate data "IMM1.phi.H" of the next instruction word from a memory, not shown. At the time T4, the immediate data of the next instruction word is read from the memory and then +1 is added to the content of the first pointer 20 in the second adder 23 so as to become "2". At the time T5, since the content of the first pointer 20 is "2", the bus interface means 71 decides that the immediate data of the 2-word instruction word requested by the executing means 74 is read in the instruction first-reading buffer 18 and decodes the content "2" of the second pointer 21 by the second decoder and turns on the gate 70a of the second shifter 70 so as to read out the 2-word length immediate data from the word positions 18a and 18c of the instruction first-reading buffer 18. In response to the reception of the 2-word length immediate data, the executing means 74 performs, under the control of the instruction interpreting means 72, the addition of the immediate data and the data of the register number RX of the register file 37 [RX+IMM1.phi. (2-word length immediate data IMM1.phi.L, IMM1.phi.H)]. A this time, the instruction interpreting means 72 controls the data expansion means 73 so that the 2-word length immediate data passes as it is. On the other hand, bus interface means 71 successively reads the instruction words from the memory if the instruction first-reading buffer 18 makes a vacancy by at least one word. After the time T5, the content "2" of the first pointer 20 and the content "2" of the second pointer 21 are added to each other in the first adder 22 so that the output of the first adder becomes "4". This "4" is decoded in the first decoder 25 and the gate 17b of the first shifter 17 is ON-controlled. As a result, the next instruction word is read in the word portion 17b of the instruction first-reading buffer 17.
Since in the conventional microcomputer the word lengths of the instruction word to be used as described above are not uniform, it is required that the identification field of the instruction word having the immediate data, offset data and others is equipped with the information indicative of the word number of the word lengths such as the immediate data and offset data, whereby the first-reading control of the microcomputer becomes complicated and the circuit arrangement also becomes complicated so as to provide a problem that the calculation processing speed becomes low.